Design of energy-efficient application-specific set by Tilman Glökler

By Tilman Glökler

After a quick advent to low-power VLSI layout, the layout house of ASIP guideline set architectures (ISAs) is brought with a different specialize in vital positive aspects for electronic sign processing. in keeping with the levels of freedom provided via this layout house, a constant ASIP layout move is proposed: this layout movement begins with a given software and makes use of incremental optimization of the ASIP undefined, of ASIP coprocessors and of the ASIP software program by utilizing a top-down method and by way of utilizing application-specific transformations on all degrees of layout hierarchy. A wide variety of real-world sign processing purposes serves as motor vehicle to demonstrate every one layout determination and gives a hands-on method of ASIP layout. ultimately, whole case experiences show the feasibility and the potency of the proposed method and quantitatively evaluation some great benefits of ASIPs in an business context.

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1: Short-Circuit Current in a CMOS Inverter Cl . It is caused by the power needed to charge and discharge (in most cases parasitic) capacitances on the chip. The switching probability αnode (also referred to as toggle activity or as toggle probability) of a single node is defined as the ratio of the number of transitions of the considered logic node to the number of clock transitions within the simulation interval. For strictly synchronous design style using positive (negative) clock edge triggered flip-flops, a logic node transition can only occur after the rising (falling) edge of the clock, thus, the maximum transition probability for a logic node without glitches is α = 12 .

A synthesizable VHDL description for non-programmable processors as well as an optimally configured instance of a VLIW processor called HPL-PD [137] is generated. The approach is limited to this processor type with a fixed instruction set, but it supports different memory and cache configurations. Satsuki is a design environment, which uses a moderately parameterizable processor template as target architecture. Parameters of this template are data path width, number of registers and instruction and data memory size.

Modularization or horizontal partitioning of design tasks, on the other hand, reduces the design time in combination with concurrent engineering (see below). • Design automation in combination with abstraction and appropriate tool support both for design and verification enables to reduce the risk of design errors and to speed up the design process. • Debugging on all levels of abstraction should be facilitated by a transparent design methodology and appropriate modeling styles. • Design reuse is also a means to reduce design time.

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Design of energy-efficient application-specific set by Tilman Glökler
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