Exploitation of Fine-Grain Parallelism by Günter Böckle

By Günter Böckle

Many parallel machine architectures are specially suited to specific sessions of functions. despite the fact that, there are just a few parallel architectures both like minded for normal courses. a lot attempt is invested into study in compiler thoughts to make programming parallel machines easier.
This e-book offers equipment for automated parallelization, in order that courses don't need to to be adapted for particular architectures; right here the focal point is on fine-grain parallelism, provided through such a lot new microprocessor architectures. The publication addresses compiler writers, machine architects, and scholars by means of demonstrating the manifold complicated relationships among structure and compiler technology.

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The funnel-file system is insofar no full multiport memory as only one value can be written into a given funnel file per cycle. However, collisions are determined by the compiler and solved by scheduling the operations accordingly. 4 LIFE (Philips/Signetics) 25 Multiport Memory lit ALU 2 ALU 1 _] t ot I I InM~ I ] I ~ / Conslnt I Instruction Issue Register Figure 13: LIFE Processor Architecture ([Slavenburg/Labrousse 90]) I] ill II 111 111 Reg. Reg. Reg. 11! ,k [Reg. Reg. Reg. File File File i Reg.

However, accesses to multiple memory modules have to be distributed among these modules so that not all memory accesses are addressed to one single memory module for particular applications. g. by using (pseudo-) randomly interleaved memory modules like in the Cydra or by assigning random addresses. Since memory access is a major bottleneck, as much information as possible should reside in registers. This holds for scalar processors, too, but on the one hand, the problem is harder for fine-grain parallel processors since we have more processing elements to feed while, on the other hand, for VLIW processors it is easier to address more registers because we can increase the number of bits to address registers in an instruction word.

File File File Functional Unit #2 Functional Unit #6 -~-TT Functiomd r Unit#11I Figure 14: LIFE Muitiport Memory ([Slavenburg/Labrousse 90]) The instruction set is rather small, comprising about 40 operations. Memory is accessed via read and write operations and the register file (used as a functional uni0 is accessed via "readreg" and "writereg" operations. The instruction word has a length of 200 bits for the six functional units and each clock cycle a new instruction may be issued. The LIFE architecture is customizable for specific applications.

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Exploitation of Fine-Grain Parallelism by Günter Böckle
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