High-speed CMOS Circuits for Optical Receivers by Jafar Savoj

By Jafar Savoj

With the exponential development of the variety of net nodes, the quantity of the information transported at the spine has elevated with an identical development. the weight of the worldwide net spine will quickly elevate to tens of terabits in step with moment. this means that the spine bandwidth standards increases through an element of fifty to a hundred each seven years. Transportation of such excessive volumes of knowledge calls for compatible media with low loss and excessive bandwidth. one of the to be had transmission media, optical fibers in achieving the easiest functionality when it comes to loss and bandwidth. High-speed info may be transported over hundreds of thousands of kilometers of single-mode fiber with out major loss in sign integrity. those fibers gradually take advantage of aid of rate and development of perf- mance. in the meantime, the digital interfaces utilized in an optical community will not be in a position to exploiting the final word bandwidth of the fiber, restricting the throughput of the community. diversified recommendations at either the approach and the circuit degrees were proposed to extend the information price of the spine. System-level strategies are in response to the usage of wave-division multiplexing (WDM), utilizing assorted colours of sunshine to transmit s- eral sequences concurrently. In parallel with that, loads of attempt has been placed into expanding the working price of the digital transceivers utilizing highly-developed fabrication approaches and novel c- cuit techniques.

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Extra info for High-speed CMOS Circuits for Optical Receivers

Example text

As shown in the waveforms, if the three signals, A, and are applied to the two XOR gates, the resulting signals will have the property of linear phase detectors. One will carry a pulse for every transition of the data with a width proportional to the phase difference between the clock and the data. The other one will have pulses as wide as half the clock period. An important feature of the Hogge phase detector is the automatic retiming of the incoming sequence. In the locked condition, the zero crossings of the clock signal appear in the middle of a bit.

26(c)). Thus the average value of is an indication of the frequency or phase difference between A and B. The sequential phase/frequency detector is a major block used for phase detection in frequency synthesizers and clock generators. Its compact and power-efficient structure makes it attractive for low-power applications. However, this circuit cannot be used to provide phase error information for random data, because in contrast to periodic data, a zero crossing at the end of each bit is not guaranteed.

The sequential phase/frequency detector (PFD) 44 HIGH-SPEED CMOS CIRCUITS FOR OPTICAL RECEIVERS proves to provide a large capture range for periodic waveforms [31]. 26(a) shows the implementation of this circuit and the correspond- ing waveforms when the two inputs have different frequencies and phases. If the frequency of input A is greater than that of input B, then the PFD Clock and Data Recovery Architectures 45 produces positive pulses at while remains zero (Fig. 26(b)). Conversely, if positive pulses appear at while If then the circuit generates pulses at either or with a width equal to the phase difference between the two inputs (Fig.

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High-speed CMOS Circuits for Optical Receivers by Jafar Savoj
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