By Landis D.
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Extra info for Programmable logic and application specific integrated circuits
Thus, mixed-signal ASICs are generally much more expensive than their digital counterparts, and design volume is quite critical in determining whether the high engineering NRE will be recovered. Thus, it is nontrivial to make the economic decision of whether to design a mixed-signal ASIC or to keep analog and digital circuits separate and have a system with more components and larger board area. Test development and test time represent a more significant cost risk in an analog/mixed signal ASIC development project than in an all digital design.
Commercial CMOS Mask Programmable Gate Array Products Company Name Family Process Technology (Drawn feature size) 37 Operating Voltage Range Max. Usable Gate Count Max. # of I/Os American Microsystems, Inc. Aspec Technology Inc. Aspec Technology Inc. 65µm Encore! 7K-500K 230,000 230,000 1,200,000 100,000 1,100,000 35,000 700,000 41,500 636,000 14,250 8200 110,000 50,000 155,000 439,000 63,000 541,000 40,000 40,000 200,000 216,000 1,094,000 200,000 560,000 32,000 200K raw gates 171,000 717,000 330 732 460 460 192 440 84 448 244 424 256 496 64 456 256 180 136-672 304-376 304-616 376-752 896 992 234 512 88 668 200 155 304 304 64 908 420 624 240 300 400 48 648 408 470 100 592 108 700 Toshiba America Electronic Comp.
This scan technique has many names: NEC calls it Scan Path; Sperry Computer Systems called it Scan/Set Logic; Honeywell Inc. 41 42 In order to provide a concrete example of a structured design for testability technique, the LSSD approach will be briefly described. A logic subsystem is said to be “Level Sensitive” when the steady-state response to any allowed input state change is independent of the circuit and wiring delays within the subsystem. Also, if an input state change involves the changing of more than one input signal, then the response must be independent of the order in which the signals change.
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